Turning to FIG. 1, a conventional SDM 100 can be seen. This SDM 100 generally comprises an integrator pipeline 114 (which generally includes stage 112-1 to 112-N coupled in series with one another), a comparator 106, and a latch 108. Each of the stages 112-1 to 112-N generally comprises an adder 102-1 to 102-N (which is typically a node for a single-ended SDM and a pair of nodes for a differential SDM), an integrator 104-1 to 104-N, and a digital-to-analog converter (DAC) 110-1 to 110-N. In operation, the integrator pipeline 114 (which helps to form an N-th order SDM) generally integrates the analog signal IN so that the comparator 106 can compare the integrated analog signal IN to one or more reference voltages. Typically, comparator 106 is comprised of several latched comparators arranged as a flash analog-to-digital converter (ADC) that perform the comparison(s) in synchronization with the clocks signal CLK (where each comparator receives at least one of the reference voltages). Usually, however, the output(s) of comparator 106 are not fully resolved digital signals, so latch 108 (which is clocked by or latches in synchronization with the inverse of the clock signal CLK) can generate fully resolved digital signals (i.e., rail-to-rail signals). The output from the latch can then be fed back to the stages 112-1 to 112-N so that these digital output(s) can be converted to analog signals and subtracted at adders 102-1 to 102-N. There are some drawbacks to this arrangement; namely, parasitic poles and/or unaccounted for excess delay (which may exist due to parasitic poles or paths) can lead to unstable behavior. Therefore, there is a need for an improved SDM.
Some other conventional circuits are: U.S. Pat. Nos. 5,729,230 6,414,615; 7,405,687; and U.S. Pat. No. 7,880,654.